The disclosed subject matter relates generally to integrated circuit device manufacturing and, more particularly, to a pattern based method for identifying design for manufacturing improvement in a semiconductor device.
The formation of various integrated circuit (IC) structures on a wafer often relies on lithographic processes, sometimes referred to as photolithography, or simply lithography. As is well known, lithographic processes can be used to transfer a pattern of a photomask (i.e., also referred to as a mask or a reticle) to a wafer. There is a pervasive trend in the art of IC fabrication to increase the density with which various structures are arranged. For example, feature size, line width, and the separation between features and lines are becoming increasingly smaller. In these sub-micron processes, yield is affected by factors such as mask pattern fidelity, optical proximity effects, and photoresist processing. Some of the more prevalent concerns include line end pullback, corner rounding and line-width variations. These concerns are largely dependent on local pattern density and topology.
Integrated circuit devices are formed in layers. Interconnect structures, such as trenches, vias, etc. are used to form interlayer connections between features, such as lines. For example, a via may be used to connect a line feature, such as a gate electrode, in a first layer to a metal line feature in another layer formed above the first layer. The accuracy at which the interconnect structures align with underlying features affects the functionality of the device. Misalignments may cause performance degradation and or device failure. Misalignment errors may arise from misregistration during the patterning processes to form the features of the various layers (i.e., the layers are not aligned accurately) or due to variations in the dimensions of the features themselves (e.g., due to proximity effects).
Integrated circuit devices are typically designed with some degree of margin to allow for some degree of misalignment. In general, increasing the margin increases the manufacturability of the device by reducing the likelihood of a yield issue. However, there is a trade-off between margin and pattern density. Increased dimensions result in decreased pattern densities. There are design rules for an integrated circuit that specify parameters such as how closely adjacent features may be formed. Design rules are specified in manner that takes into account manufacturing limitations such as overlay and/or optical proximity effects. Increasing the margin for a given feature may result in the violation of one or more of the design rules unless the spacing is increased.
During the design process various tools may be used to check the design. A design rule checker may be used to verify that none of the patterns violates a design rule. A design for manufacturability (DFM) tool may be used to generate a score for the design representing the likelihood that the device can be manufactured without pattern based yield issues. Based on DFM analysis, one or more dimensions of the design shapes may be changed to increase manufacturability. For example, a line may be may widened to provide increased overlap to increase its manufacturability. However, increasing the line width typically decreases the spacing between adjacent features. Thus, the widening is limited by spacing design rules.
DFM analysis is further complicated when multiple patterning processes are used to pattern features on the die. In double patterning, the effective spacing is decreased by patterning different sets of features on the same layer using different exposures. Multiple reticles may be used, such as one reticle for each exposure. The spacing between the features is typically less than what could be achieved suing a single reticle and a single exposure due to optical limitations.
In a single mask patterning process, the design shapes are retargeted based on a Line/Space driven look-up bias table to move in or out the polygon edges. In the context of multiple patterning, there are two or more reticles (colors) for patterning. Therefore, the layout from design is decomposed into two or more layouts (i.e., colors). There are different design rules for the shapes on the same mask (i.e., same color design rule) than for shapes on the multiple reticles (i.e., different color design rules). Retargeting using a single bias look-up table is not effective for maintaining single color and different color design rules in a multiple patterning process.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.